The present invention concerns integrated memory circuits, ferroelectric memory transistors, and methods of making these circuits and transistors.
Integrated memory circuits serve as data-storage components in thousands of products, from televisions, to automobiles, to computers. Typically, these memory circuits are implemented as arrays of floating-gate transistors, with each transistor storing an electrical charge representative of a one or a zero on its floating gate.
In recent years, these floating-gate transistors have been modified to include a layer of ferroelectric material that exhibit electric polarizations, analogous to magnetic polarizations, in response to appropriate electrical signals. One electrical signal polarizes the material to represent a zero, and another signal oppositely polarizes the material to represent a one. The polarizations affect operation of the transistors in specific ways, which enables detection of their polarization states and thus recovery of stored data. Memory circuits using these ferroelectric memory transistors enjoy advantages, such as faster write cycles and lower power requirements, over conventional floating-gate memory circuits.
The present inventors have identified at least one problem with the conventional structure of these ferroelectric memory transistors. The conventional structure includes a semiconductive layer and a multi-layer gate structure stacked atop the semiconductive layer. Built upward from the semiconductive layer, the gate structure comprises a silicon-dioxide insulative layer, a metal layer, a ferroelectric layer, and a control gate.
The problem is that the multilayer gate structure forces the insulative layer to withstand a greater portion of voltages applied to the control gate than the ferroelectric layer, even though the ferroelectric, because of its at least 100 times greater permittivity, can withstand greater voltages than the insulative layer. More precisely, the metal layer and the large difference in permittivities (or dielectric constants) of the silicon dioxide and conventional ferroelectric material (4 versus 400 or more) cause the gate structure to behave as a series connection of a small capacitor and a large capacitance, with a greater portion of any applied voltage falling across the silicon dioxide of the small capacitor than the ferroelectric layer of the large capacitor. The inventors expect this small-capacitor-large-capacitor behavior to compromise reliability as fabricators attempt to meet the demand for smaller ferroelectric memories using thinner insulative layers, which are more likely to breakdown under their disproportionate share of applied voltages.
Accordingly, there is a need for ferroelectric memories that can scale to smaller dimensions with better reliability.
To address these and other needs, the inventors devised unique ferroelectric gate structures and related fabrications methods. One exemplary gate structure includes a high-integrity silicon oxide insulative layer; a doped titanium-oxide layer; a weak ferroelectric layer; and a control gate. In contrast to the conventional gate structure, this exemplary structure replaces the metal layer between the insulative layer and the ferroelectric layer with a titanium-oxide layer and the conventional ferroelectric layer with a weak ferroelectric, reducing the permittivity mismatch across the layers and thus promoting a more balanced voltage distribution across them. This, in turn, promotes reliability of gate structures with thinner gate insulation.
An exemplary fabrication method entails forming the silicon-oxide layer in a low-temperature oxygenation process using a Krypton plasma, forming the doped titanium-oxide layer using atomic-layer deposition, and forming the weak ferroelectric from a doped zinc oxide. Exemplary dopants for the titanium-oxide layer include strontium or barium, and exemplary dopants for the zinc oxide include lithium and magnesium.